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All fields Title Creator / Publisher Keyword Year AND OR AND NOT All fields Title Creator / Publisher Keyword Year AND OR AND NOT All fields Title Creator / Publisher Keyword Year AND OR AND NOT All fields Title Creator / Publisher Keyword Year AND OR AND NOT All fields Title Creator / Publisher Keyword Year Sort by creator [A → Z]' creator [Z → A]' publishing year ↑ (asc)' publishing year ↓ (desc)' title [A → Z]' title [Z → A]' Simple Search Hits 1 – 4 of 4 1 Building an Ontology for Command & Control Curts, Raymond J.; Campbell, Douglas E. In: DTIC (2005) BASE Show details 2 Mutual Ground Alterman, Rick In: DTIC (2005) BASE Show details 3 A Dialectic for Network Centric Warfare Lambert, Dale A.; Scholz, Jason B. In: DTIC (2005) BASE Show details 4 Initial Kernel Timing Using a Simple PIM Performance Model Katz, Daniel S.; Block, Gary L.; Springer, Paul L.; Sterling, Thomas; Brockman, Jay B.; Callahan, David In: DTIC AND NTIS (2005) Abstract: This presentation will describe some initial results of paper-and-pencil studies of 4 or 5 application kernels applied to a processor-in-memory (PIM) system roughly similar to the Cascade Lightweight Processor (LWP). The application kernels are: * Linked list traversal * Sun of leaf nodes on a tree * Bitonic sort * Vector sum * Gaussian elimination The intent of this work is to guide and validate work on the Cascade project in the areas of compilers, simulators, and languages. We will first discuss the generic PIM structure. Then, we will explain the concepts needed to program a parallel PIM system (locality, threads, parcels). Next, we will present a simple PIM performance model that will be used in the remainder of the presentation. For each kernel, we will then present a set of codes, including codes for a single PIM node, and codes for multiple PIM nodes that move data to threads and move threads to data. These codes are written at a fairly low level, between assembly and C, but much closer to C than to assembly. For each code, we will present some hand-drafted timing forecasts, based on the simple PIM performance model. Finally, we will conclude by discussing what we have learned from this work, including what programming styles seem to work best, from the point-of-view of both expressiveness and performance. ; See also ADM001742. Presented at the Annual High Performance Embedded Computing (HPEC) Workshops (8th) held in Lexington, MA on 28-30 Sep 2004. HPEC-7-VOL-1-REV. Prepared in cooperation with Notre Dame University and Cray, Inc. The original document contains color images. Briefing charts only. Keyword: *MATHEMATICAL MODELS; *PROCESSING EQUIPMENT; BRIEFING CHARTS; COMPILERS; COMPONENT REPORTS; Computer Hardware; LIGHTWEIGHT; LOW LEVEL; NODES; Operations Research; PIM(PROCESSOR-IN-MEMORY); SIMULATORS; SYMPOSIA URL: http://www.dtic.mil/docs/citations/ADA433091 http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA433091 BASE Hide details

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