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1	Enhancing a Web Crawler with Arabic Search Capability
	Nguyen, Qui V
	In: DTIC (2010)
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2	Blog Fingerprinting: Identifying Anonymous Posts Written by an Author of Interest Using Word and Character Frequency Analysis
	Dreier, David J.
	In: DTIC (2009)
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3	An Analysis of Specware and Its Usefulness in the Verification of High Assurance Systems
	DeCloss, Daniel P.
	In: DTIC (2006)
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4	Speeding Up a Path-Based Policy Language Compiler
	Guven, Ahmet
	In: DTIC AND NTIS (2003)
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5	An Architecture for the Semantic Processing of Natural Language Input to a Policy Workbench
	Custy, E. J.
	In: DTIC AND NTIS (2003)
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6	Automatic Verification of Multiagent Conversations
	Lacey, Timothy; DeLoach, Scott A.
	In: DTIC (2000)
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7	Generalized Aliasing as a Basis for Program Analysis Tools
	O'Callahan, Robert
	In: DTIC (2000)
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8	Turtle Graphics Implementation Using a Graphical Dataflow Programming Approach
	Lovejoy, Robert S.
	In: DTIC AND NTIS (1992)
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9	Global Optimization of Digital Circuits.
	Flandera, Richard
	In: DTIC AND NTIS (1991)
	Abstract: This thesis was divided into two tasks. The first task involved developing a parser which could translate a behavioral specification in Very High-Speed Integrated Circuits (VHSIC) Hardware Description Language (VHDL) into the format used by an existing digital circuit optimization tool, BOolean Reasoning In Scheme (BORIS). Since this toll is written in Scheme, a dialect of Lisp, the parser was also written in Scheme. The parser was implemented is Artez's modification of Earley's Algorithm. Additionally, a VHDL tokenizer was implemented in Scheme and a portion of the VHDL grammar was converted into the format which the parser uses. The second task was the incorporation of intermediate functions into BORIS. The existing BORIS contains a recursive optimization system that optimizes digital circuits by using circuit outputs as inputs into other circuits. Intermediate functions provide a greater selection of functions to be used as circuits inputs. Using both intermediate functions and output functions, the costs of the circuits in the test set were reduced by 43%. This is a 10% reduction when compared to the existing recursive optimization system. Incorporating intermediate functions into BORIS required the development of an intermediate-function generator and a set of control methods to keep the computation time from increasing exponentially.
	Keyword: Computer aided design; Digital circuits; ALGORITHMS; BEHAVIOR; BOOLEAN ALGEBRA; BORIS(Boolean Reasoning In Scheme); CIRCUITS; COMPUTATIONS; Computer Programming and Software; CONTROL; COSTS; DIGITAL SYSTEMS; Earley algorithm; Electrical and Electronic Equipment; Electricity and Magnetism; FUNCTIONS; HIGH RATE; INTEGRATED CIRCUITS; LANGUAGE; OPTIMIZATION; OUTPUT; PARSERS; REASONING; RECURSIVE FUNCTIONS; SPECIFICATIONS; TEST SETS; THESES; TIME; TOOLS; VHDL(VHSIC Hardware Descriptor Language); VHSIC(Very High Speed Integrated Circuits)
	URL: http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA243740 http://www.dtic.mil/docs/citations/ADA243740
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10	A Non-Cognitive Formal Approach to Knowledge Representation in Artificial Intelligence.
	McMannama,Jim A
	In: DTIC AND NTIS (1986)
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