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Hits 101 – 120 of 383

101
Automatic Tools for Developing Fine-Grained Signal Processing Programs on Multicomputers.
In: DTIC AND NTIS (1995)
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102
Eucalyptus: Integrating Natural Language Input with a Graphical User Interface
In: DTIC AND NTIS (1994)
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103
Course-of-Action Selection Tool (COAST)
In: DTIC AND NTIS (1994)
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104
Semiautomatic Deabbreviation of Source Programs
In: DTIC AND NTIS (1994)
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105
Corpora and Data Preparation
In: DTIC (1993)
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106
Language Interoperability Issues in the Integration of Heterogeneous Systems
In: DTIC (1993)
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107
Corpora and Data Preparation for Information Extraction
In: DTIC (1993)
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108
The State Transition Diagram with Path Priority and It's Applications
In: DTIC AND NTIS (1993)
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109
Maygen: A Symbolic Debugger Generation System
In: DTIC AND NTIS (1993)
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110
An Evaluation Methodology for Natural Language Processing Systems
In: DTIC AND NTIS (1992)
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111
Turtle Graphics Implementation Using a Graphical Dataflow Programming Approach
In: DTIC AND NTIS (1992)
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112
Proceedings of the Annual Ada Software Engineering Education and Training Symposium (6th), Held in Alexandria, Virginia on September 11-13, 1991
In: DTIC AND NTIS (1991)
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113
The Pegasys Environment for Graphical Documentation of Large Programs
In: DTIC AND NTIS (1991)
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114
Netlist +: A Simple Interface Language for Chip Design
In: DTIC AND NTIS (1991)
Abstract: NetList (+) is a design specification language developed at MOSIS for rapid turn-around cell-based ASIC prototyping. By using NetList (+), a uniform representation is achieved for the specification, simulation, and physical description of a design. Our goal is to establish an interfacing methodology between design specification and independent computer aided design tools. Designers need only to specify a system by writing a corresponding netlist. This netlist is used for both functional simulation and timing simulation. The same netlist is also used to derive the low level physical tools to generate layout. Another goal of using NetList (+) is to generate parts of a design by running it through different kinds of placement and routing (P&R) tools. For example some parts of a design will be generated by standard cell P&R tools. Other parts may be generated by a layout tiler -- i.e. datapath compiler, RAM/ROM generator, or PLA generator. Finally all different parts of a design can be integrated by general block P&R tools as a single chip. The NetList (+) language can actually act as an interface among tools. Section 2 shows a flowchart to illustrate the NetList (+) system and its relation with other related design tools. Section 3 shows how to write a NetList (+) description from the block diagram of a circuit. In section 4 discusses how to prepare a cell library or several cell libraries for a design system. Section 5 gives a few designs by NetList (+) and shows their simulation and layout results in the appendix.
Keyword: *COMPUTER AIDED DESIGN; *INTEGRATED CIRCUITS; *PROGRAMMING LANGUAGES; CELLS; CHIPS(ELECTRONICS); COMPILERS; Computer Programming and Software; DIAGRAMS; Electrical and Electronic Equipment; FLOW CHARTING; INTERFACES; LANGUAGE; LIBRARIES; LOW LEVEL; PHYSICAL PROPERTIES; SIMULATION; SPECIFICATIONS; TIME; TOOLS; WRITING
URL: http://oai.dtic.mil/oai/oai?&verb=getRecord&metadataPrefix=html&identifier=ADA236444
http://www.dtic.mil/docs/citations/ADA236444
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115
Global Optimization of Digital Circuits.
In: DTIC AND NTIS (1991)
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116
Software Technology for Adaptable, Reliable Systems (STARS): Peer Review Capability Description
In: DTIC AND NTIS (1990)
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117
Northeast Artificial Intelligence Consortium (NAIC). Volume 18. A distributed Artificial Intelligence Approach to Information Fusion and Object Classification
In: DTIC AND NTIS (1990)
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118
Computer-Based Instruction Authoring Tools System (CATS): User's Manual.
In: DTIC AND NTIS (1990)
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119
Using the Feature Exchange Language in the Next Generation Controller
In: DTIC AND NTIS (1990)
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120
The hierarchical development of a generic type mechanism for functional languages
Bailes P.A.. - : Elsevier BV, 1990
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