2 |
PACSafe: Leveraging ARM Pointer Authentication for Memory Safety in C/C++ ...
|
|
|
|
BASE
|
|
Show details
|
|
3 |
Compiler-Driven Simulation of Reconfigurable Hardware Accelerators ...
|
|
|
|
BASE
|
|
Show details
|
|
5 |
How ISO C became unusable for operating systems development ...
|
|
|
|
BASE
|
|
Show details
|
|
6 |
Quickstrom: Property Based Acceptance Testing with LTL Specifications ...
|
|
|
|
BASE
|
|
Show details
|
|
7 |
POLYCRUISE: A Cross-Language Dynamic Information Flow Analysis ...
|
|
|
|
BASE
|
|
Show details
|
|
8 |
POLYCRUISE: A Cross-Language Dynamic Information Flow Analysis ...
|
|
|
|
BASE
|
|
Show details
|
|
9 |
A Systematic Evaluation of Large Language Models of Code ...
|
|
|
|
BASE
|
|
Show details
|
|
10 |
On Reinforcement Learning, Effect Handlers, and the State Monad ...
|
|
|
|
BASE
|
|
Show details
|
|
11 |
Compilable Neural Code Generation with Compiler Feedback ...
|
|
|
|
BASE
|
|
Show details
|
|
13 |
Threaded Code Generation with a Meta-Tracing JIT Compiler ...
|
|
|
|
BASE
|
|
Show details
|
|
15 |
Svar: A Tiny C++ Header Brings Unified Interface for Multiple programming Languages ...
|
|
|
|
BASE
|
|
Show details
|
|
16 |
Elastic Silicon Interconnects: Abstracting Communication in Accelerator Design ...
|
|
|
|
BASE
|
|
Show details
|
|
17 |
Pifthon: A Compile-Time Information Flow Analyzer For An Imperative Language ...
|
|
|
|
BASE
|
|
Show details
|
|
18 |
HIR: An MLIR-based Intermediate Representation for Hardware Accelerator Description ...
|
|
|
|
BASE
|
|
Show details
|
|
|
|